SNAP

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Contents

Renamed: Smart Network ADC Processor (SNAP)

Developers

NRAO: Rich Bradley, Joe Greenberg, Rich Lacasse, Robert Treacy

UC Berkeley: Dave DeBoer, Jack Hickish, Aaron Parsons, Dan Werthimer


Description

We have developed a low-cost FGPA board with on board ADCs, frequency synthesizer, and two 10Gbit Ethernet ports. This board is intended for digitizing data at each telescope of a large array, time stamping the data, and sending the ADC time domain data over Ethernet to a central computing facility. The board was designed for the Hydrogen Epoch of Reionization Array (HERA).

The board could also be used as a low cost CASPER ADC and signal processing board for education and low to mid performance instrumentation.


Status

  • 2014aug19: The PO for the first batch of bare fabricated boards was submitted.
  • 2014sep23: The first batch of bare fabricated boards have arrived at UC Berkeley.
  • 2014nov02: 4 boards have been assembled, stuff and soldered, at least partially. Testing has started.
  • 2016aug09: 4 rev 2 boards at UCB. Several more on order. Being used for various spectrometer apps. Available to order -- email mo@digicom.org


Chipset



Draft specification

  • Power: 12-18 VDC (at chassis), approx 12-24 W


  • Inputs
    • Analog signal: 50 ohm single-ended configurable as:
      • three sets of 4 inputs at 250 Msps for a total of 12 inputs or
      • three sets of 2 inputs at 500 Msps for a total of 6 inputs or
      • three sets of 1 input at 1 Gsps for a total of 3 inputs
      • The channel-channel isolation is not as high for channels within a set as those that are in different sets.
        • channel-channel isolation neighboring channels within 1 set : TBD (guess about -30 dB)
        • channel-channel isolation separated channels within 1 set : TBD (guess about -40 dB)
        • channel-channel isolation from 1 set to another set : TBD (guess better than -40 dB)
        • See ADC16 test results for more information.
    • 1 PPS: 50 ohm single-ended LVTTL logic levels
      • Vin-high 2.0 to 3.3 Volts
      • Vin-low 0.0 to 0.8 Volts
    • External ADC clock: 50 ohm single-ended about +2 dBm
      • External ADC clock Pmax +15 dBm
      • External ADC clock Pnom +2 dBm (1.4 Vpp)
      • External ADC clock Pmin -7 dBm
    • or option to use internal frequency synthesizer
      • 10 to 100 MHz reference input for on board synthesizer: 50 ohm single-ended about +10 dBm
      • External reference Pmax +20 dBm
      • External reference Pnom +13 dBm (2.4 Vpp)
      • External reference Pmin -1 dBm
        • synthesizer output: 100 MHz to 1 GHz
        • synthesizer input: 10 MHz external ref, or IEEE1588 ref frequency.
    • phase offset and stability between boards: TBD
    • Auxillary Digital I/O:
      • ZDOK
      • various GPIO headers
      • USB UART
      • 2 10Gbit SFP+ Ethernet connectors





Data Sheets


Software Resources


Background Information

Bringup Status & Notes

A guide to bringing up a SNAP board is available here: SNAP Bringup

First report of SNAP thermal performance in RFI enclosure: File:Snap thermal report.pdf

Specification for data stored in the One-Time Programmable region of the SPI flash

ADC Calibration guide

A guide to calibrating ADCs on a SNAP board is available here: SNAP ADC Calibration

ADC Operation Info (Demux Explanation)

For a more ADC operation details check out this page: ADC operation

Binaries and SNAP-specific configuration files are available on github

Power Regulators

  • Below tested on board S/N 1 & 2
    • Programmed regulators via TI programmer: OK
    • Power use on power up 0.78A @ 12V (0.9A with Raspberry Pi)
    • TODO: Calibrate current monitoring

FPGA

  • Below tested on board S/N 2
    • Programmed via JTAG with Xilinx Platform Cable: OK
    • Programmed via Raspberry Pi using JTAG over RPI ribbon cable header: OK (code at https://github.com/jack-h/RpiJtag)
    • Programmed SPI flash via JTAG with Xilinx Platform Cable: OK @ 3 MHz config clock (NB, set S1 switches 2 and 5 to on)
    • Retested SPI flash with 50 MHz config clock (~1s to program on power up): OK
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