SNAP

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Renamed: Smart Network ADC Processor (SNAP)

Developers

NRAO: Rich Bradley, Joe Greenberg, Rich Lacasse, Robert Treacy

UC Berkeley: Zuhra Abdurashidova, Dave DeBoer, Jack Hickish, Aaron Parsons, Dan Werthimer


Description

We have developed a low-cost FGPA board with on board ADCs, frequency synthesizer, and two 10Gbit Ethernet ports. This board is intended for digitizing data at each telescope of a large array, time stamping the data, and sending the ADC time domain data over Ethernet to a central computing facility. The board was designed for the Hydrogen Epoch of Reionization Array (HERA).

The board could also be used as a low cost CASPER ADC and signal processing board for education and low to mid performance instrumentation.


Status

  • 2014aug19: The PO for the first batch of bare fabricated boards was submitted.
  • 2014sep23: The first batch of bare fabricated boards have arrived at UC Berkeley.
  • 2014nov02: 4 boards have been assembled, stuff and soldered, at least partially. Testing has started.
  • 2016aug09: 4 rev 2 boards at UCB. Several more on order. Being used for various spectrometer apps. Available to order -- email mo@digicom.org


Chipsets


  • FPGA
    • Xilinx Kintex7 web site: XC7K160T-2FFG676C
    • As shown in the BOM, with suitable bypass capacitor changes, the XC7K325T-2FFG676C and XC7K410T-2FFG676C are supported by the PCB


Draft specification

  • Power: 12 to 24Watts (as a function of operations performed, cards installed at the ZDok+ connector, etc)
    • Vin measured at J2 input: 12 +/- approx. 1 VDC. 11 to 13VDC.
    • The actual minimum Vin is unknown.
      • It may be considerably above the Vin min limit suggested by the TI power modules (shown above) ~5.5V (from the VCC5V0 generator U20) due to changes in component heating or voltage drop which increase with increased current.
    • The maximum Vin is set by the TI power modules (shown above) 14VDC. The value of 13VDC was shown above for margin.
    • Virtually all initial lab tests have been performed with Vin = 12 +/- 0.2VDC.


  • Inputs
    • Analog signal for the ADCs. 50 ohm single-ended configurable as:
      • SMATP1 through SMATP12
      • 1 set of inputs for each HMCAD1511 ADC IC. There are 3 ADC ICs per board thus there are 3 analog input sets per board.
      • Three sets of 4 inputs at 250 Msps for a total of 12 inputs or
      • Three sets of 2 inputs at 500 Msps for a total of 6 inputs or
      • Three sets of 1 input at 1 Gsps for a total of 3 inputs
      • The sample clocks delivered to the ADC ICs are copies of the same signal.
      • In the typical operation the 3 ADC ICs will be configured into the same 4, 2 or 1 input channel mode.
      • With suitable FPGA gateware, and using the clock divider logic within the ADC ICs, it may be possible to operate the ADC ICs in multiple input channel modes. This has not been tried.
      • The full scale inputs to the Analog Devices ADC IC are (assuming single input into 50 ohm load)
        • AC coupled to (approximately) F3dB 650 MHz (typical)
        • 2 Vpeak_to_peak (+10 dBm) sine wave
        • -2.6 dBm gaussian noise w/ crest factor 6
      • Due to the loss in the components just upstream of the ADC IC
        • The F3dB frequency of the board will be reduced, possibly considerably, relative to a ADC IC itself.
        • The full scale input level will be greater than that of the ADC IC itself.
      • The usable full scale range is also a function of the digital gain programmed into the ADC IC.
      • The actual ADC IC inputs are differential signals. This board has an AC coupled balun on each input to generate these differential signals. Each of the ADC IC's full scale differential inputs are :
        • -0.5 to +0.5 V (+4 dBm) sine wave
        • -8.5 gaussian noise w/ crest factor 6
        • centered around the around the ADC IC's Vcommon of AVDD/2 = 1.8V/2 = 0.9V
        • +0.4 to +1.4 V (at the 2 ADC IC input pins)
        • The input circuitry, including balun and shunt caps, have been selected for low frequency inputs (approx 4.5 MHz to 200 MHz). Different valued discrete components will need to be installed for optimal frequency response in different frequency ranges.
      • The channel-channel isolation is not as high for channels within a set (IC) as those that are in different sets (ICs).
        • channel-channel isolation neighboring channels within 1 set : TBD (guess about -30 dB)
        • channel-channel isolation separated channels within 1 set : TBD (guess about -40 dB)
        • channel-channel isolation from 1 set to another set : TBD (guess better than -40 dB)
        • See ADC16 test results for more information.
    • Digital 1 PPS: 50 ohm single-ended LVTTL logic levels
      • SMATP13
      • Vin-high 2.0 to 3.3 Volts. Low current drive sources, such as typical LVTTL or CMOS gates, probably can not supply the 40mA required to supply the 2.0V into the 50ohm load.
      • Vin-low 0.0 to 0.8 Volts
    • External ADC clock: 50 ohm single-ended about +2 dBm
      • SMATP15
      • External ADC clock Pmax +15 dBm
      • External ADC clock Pnom +2 dBm (1.4 Vpp)
      • External ADC clock Pmin -7 dBm
    • External reference for on-board frequency synthesizer: 50 ohm about +10dBm
      • SMATP14
      • Actual input impedance : TBD. The PCB includes circuits to square the waveform and overload protection.
      • External reference Pmax +20 dBm
      • External reference Pnom +13 dBm (2.4 Vpp)
      • External reference Pmin -1 dBm
      • At the TI LMX2581 IC pins
        • maximum with VCC applied : 1.8Vpp or ~ +9dBm
        • maximum without VCC applied : 1.0Vpp or ~ +4dBm
        • minimum : 0.4Vpp or ~ -4 dBm
      • 10 to 100 MHz, or IEEE1588 ref.
      • phase offset and stability between boards: TBD
  • Outputs
    • TP2: synthesizer output: 100 MHz to 1 GHz
      • levels: TBD
      • This vertical launch SMA receptacle is located in the middle of the PCB. It is not located on the same edge of the PCB as the other 15 coax inputs and 1 coax output.
    • SMTAP16: FPGA output OUT1PPS buffered by 7 ports of TI SN74LVCC4245A buffer with 50 ohm source series resistor. This need not be programmed as 1PPS.
      • Vout-high : approx. 4.6V into 50 ohm load. Approx 4.9V into high impedance load.
      • Vout-low  : approx. 0.4V into 50 ohm load. Aprrox 0.2V into high impedance load.
  • Auxillary Digital I/O
      • ZDok+
        • P3: Routed on the PCB as 40 differential pairs but can also be 80 single-ended programmable IOs
          • The IO bank VCCO is 2.5V which means these IO outputs are supported : LVDS_25, LVCMOS25, PPDS_25 (point-to-Point Differential Signaling, RSDS_25 (reduced swing differential signaling).
          • A number of different, additional, IO standards are supported as inputs to the FPGA (only inputs to the FPGA) such as HSTL
      • various GPIO headers
        • J2 2x6 header with 2 grounds and 10 GPIOs TEST0..TEST9
          • outputs from the FPGA to J2
            • See page 14 of the schematics for GPI connector J9,
            • See page 12 for the VCCO voltages supplied to the different banks.
            • TEST0..6 : High Range bank 14, VCCO=2.5V Vref pins: NC, ZDok+ signal
              • TEST0,1 are a differential FPGA pin pair.
              • TEST2,3 are a differential FPGA pin pair.
              • TEST4,5 are a differential FPGA pin pair.
            • TEST7  : High Range bank 13, VCCO=2.5V Vref pins: NC, NC
            • TEST8..9 : High Range bank 15, VCCO=3.3V Vref pins: NC, P12 signal
              • TEST8,9 are a differential FPGA pin pair.
            • The 10 TEST0..9 nets look to be routed individually w/ various trace widths and not as controlled impedance differential pairs.
            • Outputs from 2.5V VCCO FPGA banks 13 and 14 to J9: TEST0..TEST7
              • Can be programmed to the following different signalling protocols. This is as set by the Xilinx FPGA. There may be additional and artificial software or design tools barriers to selecting 1 or more of these output types :
                • LVDS_25 Low Voltage Differential Signaling. 100 ohm parallel termination.
                • MINI_LVDS_25 Mini LVDS a psuedo-standard for flat panel displays. 100 ohm parallel termination.
                • LVCMOS25 Low Voltage Complementary Metal-Oxide semiconductor. 0 to 2.5V. Birectional. Fast and Slow slew rate and drive strengths 4, 8, 12, and 16mA. High current may need parallel termination to VCCO/2.
                • PPDS_25 Point-to-Point Differential Signaling.
                • RSDS_25 Deduced Swing Differential Signaling.
                • BLVDS Bus Low Voltage Differential Signaling. This is a non standard bidirectional differential interface. It requires a very particular termination network.
            • Outputs from 3.3V VCCO FPGA to J9: TEST8..TEST9
              • Can be programmed to the following different signalling protocols. This is as set by the Xilinx FPGA. There may be additional and artificial software or design tools barriers to selecting 1 or more of these output types :
                • LVCMOS33 Low Voltage Complementary Metal-Oxide semiconductor. 0 to 2.5V. Birectional. Fast and Slow slew rate and drive strengths 4, 8, 12, and 16mA. High current may need parallel termination to VCCO/2.
                • LVTTL Low Voltage Transistor Transistor Logic. JEDEC JESD 8C.01. Implemented with a push-pull output buffer Fast and Slow slew rate and drive strengths 4, 8, 12, 16, and 24mA. Higher current versions may need parallel termination to VCCO/2. Voh might be much higher than 2.4V for lightly loaded circuits.
                • PCI33_3 Peripheral Component Interconnect. 3.3V (not 5V). This might have large swing large drive and thus may be hard to tame.
                • TMDS_33 Transition Minimized Differential Signaling. Used by DVI and HDMI interfaces. 50 ohm pull-up to 3.3V is required at the end of ther transmission line.
          • inputs to the FPGA from J2
        • P12 2x20 with a collection of GPIOs
      • USB UART
      • Two (2) 10Gbit SFP+ Ethernet connectors



  • Schematics v2.1
    • v2.0 fixes ZDok+ connector and power connector footprints, as well as minor bugfixes and improvements. See sheet 7 of the schematics for details.
    • v2.1 fixes FPGA temp/voltage monitoring. See sheet 7 of the schematics for details.
    • PDF schematics: File:DAB-HERALD Schematic revC.pdf or direct link schematics (pdf)
      • Warning: The ASCII art diagram of showing the ZDok+ connector pin locations on page 27 is not correct for a bird's eye view of the top of the board. It has signal pins reversed; A1 and A20 should be swapped. The ASCII art drawing on page 7 is correct.
      • Warning: The comments on page 9 stating that the VCCO of the IO banks for the ZDok+ signal pins will probably be 3.3V and on bank 16 are incorrect. The diagram and changes for Rev B comment on page 7 are correct: the banks are 12, 13 and 14 and the voltage is 2.5V. The comment on page 12 that VADJ_FPGA probably set to 2.5V is also correct.
    • Zipped Orcad Schematics of SNAP Board: File:DAB-HERALD orcad revC.zip
    • ASCII text netlist (Mentor PADS format) File:DAB-HERALD Schematic revC netlist.txt direct linke netlist (ASCII text)



Data Sheets


Software Resources


Background Information

Bringup Status & Notes

A guide to bringing up a SNAP board is available here: SNAP Bringup

First report of SNAP thermal performance in RFI enclosure: File:Snap thermal report.pdf

First report of SNAP RFI performance in RFI enclosure: SNAPRFITestReport (pdf)

Specification for data stored in the One-Time Programmable region of the SPI flash

ADC Calibration guide

A guide to calibrating ADCs on a SNAP board is available here: SNAP ADC Calibration

ADC Operation Info (Demux Explanation)

For a more ADC operation details check out this page: ADC operation

Binaries and SNAP-specific configuration files are available on github

Power Regulators

  • Below tested on board S/N 1 & 2
    • Programmed regulators via TI programmer: OK
    • Power use on power up 0.78A @ 12V (0.9A with Raspberry Pi)
    • TODO: Calibrate current monitoring

FPGA

  • Below tested on board S/N 2
    • Programmed via JTAG with Xilinx Platform Cable: OK
    • Programmed via Raspberry Pi using JTAG over RPI ribbon cable header: OK (code at https://github.com/jack-h/RpiJtag)
    • Programmed SPI flash via JTAG with Xilinx Platform Cable: OK @ 3 MHz config clock (NB, set S1 switches 2 and 5 to on)
    • Retested SPI flash with 50 MHz config clock (~1s to program on power up): OK
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