Renamed: Smart Network ADC Processor (SNAP)
NRAO: Rich Bradley, Joe Greenberg, Rich Lacasse, Robert Treacy
UC Berkeley: Dave DeBoer, Jack Hickish, Aaron Parsons, Dan Werthimer
We have developed a low-cost FGPA board with on board ADCs, frequency synthesizer, and two 10Gbit Ethernet ports. This board is intended for digitizing data at each telescope of a large array, time stamping the data, and sending the ADC time domain data over Ethernet to a central computing facility. The board was designed for the Hydrogen Epoch of Reionization Array (HERA).
The board could also be used as a low cost CASPER ADC and signal processing board for education and low to mid performance instrumentation.
- 2014aug19: The PO for the first batch of bare fabricated boards was submitted.
- 2014sep23: The first batch of bare fabricated boards have arrived at UC Berkeley.
- 2014nov02: 4 boards have been assembled, stuff and soldered, at least partially. Testing has started.
- 2016aug09: 4 rev 2 boards at UCB. Several more on order. Being used for various spectrometer apps. Available to order -- email firstname.lastname@example.org
- 3 each of Hittite HMCAD1511 web site quad ADC
- Xilinx Kintex7 web site: XC7K160T-2FFG676C
- Raspberry PI web site Add-on board connected via 40-pin ribbon cable.
- Frequency synthesizer
- Power: 12-18 VDC (at chassis), approx 12-24 W
- Power Dissipation Information: File:SNAP BOM with Power Diss.xlsx.zip
- Analog signal: 50 ohm single-ended configurable as:
- three sets of 4 inputs at 250 Msps for a total of 12 inputs or
- three sets of 2 inputs at 500 Msps for a total of 6 inputs or
- three sets of 1 input at 1 Gsps for a total of 3 inputs
- The channel-channel isolation is not as high for channels within a set as those that are in different sets.
- channel-channel isolation neighboring channels within 1 set : TBD (guess about -30 dB)
- channel-channel isolation separated channels within 1 set : TBD (guess about -40 dB)
- channel-channel isolation from 1 set to another set : TBD (guess better than -40 dB)
- See ADC16 test results for more information.
- 1 PPS: 50 ohm single-ended LVTTL logic levels
- Vin-high 2.0 to 3.3 Volts
- Vin-low 0.0 to 0.8 Volts
- External ADC clock: 50 ohm single-ended about +2 dBm
- External ADC clock Pmax +15 dBm
- External ADC clock Pnom +2 dBm (1.4 Vpp)
- External ADC clock Pmin -7 dBm
- or option to use internal frequency synthesizer
- 10 to 100 MHz reference input for on board synthesizer: 50 ohm single-ended about +10 dBm
- External reference Pmax +20 dBm
- External reference Pnom +13 dBm (2.4 Vpp)
- External reference Pmin -1 dBm
- synthesizer output: 100 MHz to 1 GHz
- synthesizer input: 10 MHz external ref, or IEEE1588 ref frequency.
- phase offset and stability between boards: TBD
- Auxillary Digital I/O:
- various GPIO headers
- USB UART
- 2 10Gbit SFP+ Ethernet connectors
- Analog signal: 50 ohm single-ended configurable as:
- Schematics v1.0
- Schematics v2.1
- v2.0 fixes ZDOK connector and power connector footprints, as well as minor bugfixes and improvements. See sheet 7 of the schematics for details.
- v2.1 fixes FPGA temp/voltage monitoring. See sheet 7 of the schematics for details.
- PDF schematics: File:DAB-HERALD Schematic revC.pdf or direct link schematics (pdf)
- Zipped Orcad Schematics of SNAP Board: File:DAB-HERALD orcad revC.zip
- ASCII text netlist (Mentor PADS format) File:DAB-HERALD Schematic revC netlist.txt direct linke netlist (ASCII text)
- Reviewed Schematic with comments
- Bill of Materials
- Design Description
- Board Layout/Design Files
- Enclosure Files
- Analog Devices ADP123AUJZ-R7 adjustable voltage regulator web site or ADP123 data sheet (pdf)
- Generates the SPI Flash's 2.8V data sheet from 5V
- Avago HSMS-2812 schottky diode web site or Avago HSMS-2818 data sheet (pdf)
- Synthesizer oscillator waveform squaring and input protection diodes
- Avago HSMS-2818 schottky diode web site or AVago HSMS-2818 data sheet (pdf)
- Clock input protection diodes
- Hittite HMCAD1511 ADC web site or HMCAD1511 data sheet (pdf)
- Analog to digital converter.
- Hittite HMC976LP3E low noise voltage regulator web site or HMC976LP3E data sheet (pdf)
- Two of these are used to generate, from 5V, the 3.3V required for the LMX2581 Synthesizer and HMC987 clock fanout buffer.
- Hittite HMC922LP4E non-reflective SPDT switch web site or HMC922LP4E data sheet (pdf)
- Select between the external sample clock and the on board LMX2581 synthesizer output.
- Hittite HMC987LP5E clock fanout buffer web site or HMC987LP5E data sheet (pdf)
- Generate 4 identical copies of the sample clock for the 3 ADC ICs and the FPGA.
- MiniCircuits balun TC1-1-13MG2 web site or balun TC1-1-13MG2+ data sheet (pdf)
- This same balun is used for both the analog inputs to be sampled as well as the external clock.
- Murata BNX016-01 15 amp LC filter (pdf)
- http://industrial.panasonic.com/www-cgi/jvcr13pz.cgi?E+PZ+3+AOJ0002+EXB24AT3AR3X+7+WW Panasonic 3dB attenuator web site] or EXB-24AT3AR3X data sheet (pdf)
- Analog input fixed attenuation and impedance matching.
- SiT9102 differential output oscillator web site or SiT9102 data sheet (pdf)
- SiT9102AI-243N25E200.00000 200 MHz LVDS oscillator for FPGA system clock
- SiT9120AI-2D3-33E156.250000 156.25 MHz LVDS oscillator for 10GbE SFP+ Ethernet
- Synergy TM2-1 balun web site or TM2-1 data sheet (pdf)
- The Synergy TM2-1 was considered for but was Not used on the rev 1 SNAP board.
- TI LP3856 3A regulator web site or LP3856 data sheet (pdf)
- Generates 1.8V for the ADC IC outputs to the FPGA from the on-board generated 2.5V.
- TI's LMX2581 synthesizer web site or LMX2581 data sheet (pdf)
- Programmable ADC sample clock generator locked to externally supplied reference.
- TI LMZ12002TZ-ADJ 2A adjustable switcher web site or direct link LMZ12002TZ-ADJ data sheet (pdf)
- The TI LMZ12002TZ-ADJ was considered for but was Not used on the rev 1 SNAP board.
- LMZ31710 10Amp power module web site or LMZ31710 data sheet (pdf)
- Generates 5V from externally supplied 12V. The 5V is used to power regulators, boards installed at the ZDok+ connector, and so on.
- PTD08A010W single 10Amp power module web site or PTD08A010W datasheet (pdf)
- Under the direct control of an UCD9248 power controller generates VCCAUXMGT form the externally supplied 12V.
- PTD08A010W single 20Amp power module web site or PTD08A010W datasheet (pdf)
- Under the direct control of an UCD9248 power controller generates VCCINT form the externally supplied 12V.
- PTD08D210W dual 10Amp power module web site or PTD08D210W data sheet (pdf)
- Under the direct control of two (2) UCD9248 power controller components, three (3) of the PTD08D210W parts generate 2.5V, FPGA's BRAM VCC, MGTA VCC and VTT from the externally supplied 12V.
- TI's UCD9248 power controller web site or UCD9248 data sheet (pdf)
- Two (2) UCD9248 parts control two (3) PTD08D210W, one (1) PTD08D020W and one (1) PTD08A010W parts to generate VCCINT, 2.5V, FPGA's BRAM VCC, MGTA VCC, VTT and VCCAUXMGT from the externally supplied 12V.
- Xilinx Kintex 7
- Fusion Digital Power Designer for programming UCD9248 power controllers.
Bringup Status & Notes
A guide to bringing up a SNAP board is available here: SNAP Bringup
First report of SNAP thermal performance in RFI enclosure: File:Snap thermal report.pdf
ADC Calibration guide
A guide to calibrating ADCs on a SNAP board is available here: SNAP ADC Calibration
ADC Operation Info (Demux Explanation)
For a more ADC operation details check out this page: ADC operation
Binaries and SNAP-specific configuration files are available on github
- Below tested on board S/N 1 & 2
- Programmed regulators via TI programmer: OK
- Power use on power up 0.78A @ 12V (0.9A with Raspberry Pi)
- TODO: Calibrate current monitoring
- Below tested on board S/N 2
- Programmed via JTAG with Xilinx Platform Cable: OK
- Programmed via Raspberry Pi using JTAG over RPI ribbon cable header: OK (code at https://github.com/jack-h/RpiJtag)
- Programmed SPI flash via JTAG with Xilinx Platform Cable: OK @ 3 MHz config clock (NB, set S1 switches 2 and 5 to on)
- Retested SPI flash with 50 MHz config clock (~1s to program on power up): OK