Interchip Links

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The following tables contain information about the gpio block parameters for each interchip link on the BEE2s.

Contents

PFB

NAME IN/OUT BIT INDEX PACK REG. in PAD? CLK PHASE TERM. METHOD
gpio_data_out OUT 0-35 Y 0 none
gpio_sync_out OUT 36 Y 0 none

CT

NAME IN/OUT BIT INDEX PACK REG. in PAD? CLK PHASE TERM. METHOD
ct_in IN 0-35 Y 270 none
sync_in IN 36 Y 270 none
ct_out OUT 0-35 Y 0 none
sync_out OUT 36 Y 0 none

Apr 06 - Previous phase on ct_in & sync_in was 180.

FFT

NAME IN/OUT BIT INDEX PACK REG. in PAD? CLK PHASE TERM. METHOD
gpio_data_in IN 0-35 Y 180 none
gpio_sync_in IN 36 Y 180 none
gpio_ctdata_out OUT 0-35 Y 0 none
gpio_ctsync_out OUT 36 Y 0 none
gpio_pol1_out OUT 37-72 Y 0 none
gpio_sync_out OUT 73 Y 0 none

Apr 6 - Previous data_in and sync_in phase was 0.

Thresholder

NAME IN/OUT BIT INDEX PACK REG. in PAD? CLK PHASE TERM. METHOD
ct_in IN 0-35 Y 270 none
ctsync_in IN 36 Y 270 none
fft_in IN 37-72 Y 270 none
fftsync_in IN 73 Y 270 none

Apr 6 - The previous phase on all inputs was 180.

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