ADC2x1000-8

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ADC2x1000-8 v1.1

Contents

Also known as

iADC

Specifications

  • Inputs
    • Clock: 10MHz-1GHz 50Ohm 0dBm
    • Signal:
    • Sync: LVTTL (5V tolerant, (SN65LVDS1)
  • Outputs
    • 1x Tyco Z-DOK+ 40 differential pair connector
      • 8x (1x8 or 2x4) 8-bit offset binary data
      • 2x digital clocks to CASPER standard Z-DOK clock pins
  • Control/Config
    • 3-wire serial
  • Miscellaneous
    • 3.3V, 5V supply headers


Versions

  • v1.0
    • Uses Tyco M/A-COM TP-101 balun with 500kHz-1.5GHz bandwidth
    • Uses right-angle through hole SMA connectors
  • v1.1
    • Uses MiniCircuits ADTL2-18 balun with 30MHz-1.8GHz bandwidth
    • Uses end-launch surface mount SMA connectors

The recommended version to use is v1.1, unless the increased low-frequency performance is critical to your application. The analog inputs for v1.0 are routed with a balun bypass, and trace cuts are required for proper operation (see figure).

ADC2x1000-8 analog input balun bypass routing.

Upcoming Changes

Note: E2V is coming out with a new revision of their AT84AD001 ADC chip, Revision C. Revision B will be phased out this year. The Revision C ADC has some improvements (eg, better cross talk, improved ENOB...). The chip will probably work fine without any changes to our gateware, but we should test the new chip to make sure.


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