Synchronous and Asynchronous Logic

Short Topical Videos

• Introduction to D Flip Flop (Kennethkoo871229)
• Timing Diagrams (EngMicroLectures)
• See How Computers Add Numbers In One Lesson (InOneLesson)

Reference Material

• Flip-Flop (Wikipedia)

1 Basic Logic Operations

Digital logic has three basic operators, the AND, the OR and the NOT. These three operators form the basis for everything in digital logic. In fact, almost everything your computer does can be described in terms of these three operations. Fortunately, these operations are not difficult to understand, as their meanings resemble the meanings of the words as used in every day language.

There are other less common operators, such as NAND, NOR, XOR, and XNOR. Interestingly, you can build any logic operation out of a combination of NAND gates, making them the most fundamental logic element.

1.1 AND, NAND, OR, NOR, XOR, XNOR

		AND	NAND	OR	NOR	XOR	XNOR
A	B	$A\cdot B$	$!(A\cdot B)$	$A+B$	$!(A+B)$	$A\oplus B$	$!(A\oplus B)$
0	0	0	1	0	1	0	1
0	1	0	1	1	0	1	0
1	0	0	1	1	0	1	0
1	1	1	0	1	0	0	1

1.2 NOT

	NOT
A
0	1
1	0

2 Clocks and Timing

In digital electronics, wires carry a high voltage to signal 1 and a low voltage to signal 0. But what happens in between? Electronic signals, though they travel fast, do take time to arrive at their destination. It can also take a while for a wire carrying a 0 to ramp up its voltage high enough to signal a 1. When reading the state of a wire, a receiver needs to know when it is in a stable state. Likewise, a transmitter needs to know when it can change the state of the wire to send the next piece of information.

To coordinate the timing of transmission and reception, almost all digital electronics rely on a special signal called a clock to synchronize decision-making. A clock is a single-wire signal that toggles between high and low states at a fixed rate. Typically, every logic element in a synchronized system will make a decision about its next state on the rising edge of a clock (that is, when it goes from 0 to 1). Shortly after the rising edge of a clock, logic elements have the opportunity to look at their next inputs and decide what their next output will be. When the next rising clock edge occurs, a final decision is made, and all logic elements jump to their next states.

2.1 Registers (a.k.a. Flip-Flops)

The foundational element of synchronization is called a register (another name for a register is flip-flop or flop for short). The simplest register (called a D flip-flop) has two inputs: data (D) and clock (clk). Its single output (Q) is assigned the state of D, read on the rising edge of clk.

Logic elements do not always need to be clocked. For example, simple logic gates like AND, OR, NOT, XOR, and NAND can continuously read their inputs and create the appropriate outputs after a nominal delay. It is possible for signals to propagate several logic levels in the time between rising clock edges, but at some stage the output of one of these logic elements will have to be registered. Any further logic operations will have to be applied to the output of the register on the next clock.

2.2 Timing Diagrams: Setup and Hold

Timing diagram for a D flip-flop. Illustrated are clock-to-q (T_pckq$),setup($T_s$),andhold($T_h$)times.$

Registers cannot make decisions instantaneously. Flip-flops typically have a setup time during which the D input to the register must be stable before the rising edge of a clock, and a hold time after the rising edge of a clock during which the D input must remain fixed. Furthermore, there is a clock-to-Q time, which is the time it takes the value to propagate from D to Q following the rising edge of a clock. The details of these mechanisms are not important for this discussion, but understanding that signals have a limited amount of time to propagate from one register to another in order to satisfy these timing demands is essential to designing FPGA circuits.

A typical signal might begin as a 0/1 on the D input of a flip-flop when a rising clock edge occurs. A nanosecond later, that state will appear on the Q output of the flip-flop, whereupon it will travel down a wire (incurring a couple more nanoseconds of delay), through a few logic circuits (a few more nanoseconds), to arrive at the D input of another flip-flop in time to satisfy the setup time required by that register before the next rising clock edge.

For visualizing how signals are sent and recaptured through synchronous digital circuits, timing diagrams are a useful tool.