Hardware

CASPER uses reconfigurable hardware based around Xilinx FPGAs. Generally, high performance ADC boards are directly connected to Internet Break-out Boards (IBOBs) for pre-processing and packetization. BEE2 boards are high performance DSP boards which perform the signal processing. IBOBs and BEE2 boards are interconnected by high speed XAUI or 10Gb Ethernet. The next generation ADC, IBOB and BEE boards are currently being designed. See the links below for further information.

Board Descriptions

1. BEE2 Website
2. MSSGE Toolflow FAQ

Block Diagrams

1. IBOB v1.1+ Block Diagram - Posted October 2006
2. ROACH Block Diagram - Updated December 2007

Board Schematics

1. IBOB v1.0 Schematics - Posted July 2006
2. IBOB v1.1 Schematics - Posted July 2006
3. IBOB v1.2/1.3 Schematics - Posted July 2006
4. iADC v1.0 Schematics - Posted July 2006
5. iADC v1.1 Schematics - Posted February 2006
6. BEE2 v1.2 Schematics - Posted June 2007
7. IBOB expansion port pinout

Layout

Cadence Allegro board layout files are available below for CASPER-supported boards. Layouts can be opened using the Allegro Free Physical Viewer tool from Cadence, and can be downloaded here.

1. iADC v1.0 Layout - Posted June 2007
2. iADC v1.1 Layout - Posted June 2007
3. iDAC v1.0 Layout - Posted June 2007
4. BEE2 v1.1 Layout - Posted June 2007
5. BEE2 v1.2 Layout - Posted June 2007
6. IBOB v1.0 Layout - Posted June 2007
7. IBOB v1.1 Layout - Posted June 2007
8. IBOB v1.2 Layout - Posted June 2007
9. IBOB v1.3 Layout - Posted June 2007